Since 2006, I have begin power IC research, including: IC reliability (ESD and package), high and low voltage integrated process development. The research contents are closely related to the industry, and all research and development are aimed at the actual products and processes. My work all mainly focused on chip reliability optimization (ESD and packaging). The processes covers GaN on Si process, 700V (BCD process), 190V (SOI process), 18V (LDD process), 20V/40V (BCD process), 5V/3.5V/1.8V conventional CMOS process, etc.
2002-2006， UESTC， bachelor
2006-2008， UESTC， master
2008-2013， UESTC， PHD
2014.1-now， SUSTC, Teaching Engineer
HV integrations and package
GaN power device
On-chip ESD protection
 Lingli Jiang, Bo Zhang, Hang Fan, et al. ESD robustness studies on the double snapback characteristics of an LDMOS with an embedded SCR[J]. Journal of Semiconductors, 2011, 32(9):094002(1-4)
 Lingli Jiang, Hang Fan, Ming Qiao, et al. ESD characterization of a 190V LIGBT SOI ESD power clamp structure for plasma display panel applications[J]. Microelectronics Reliability, 2013, 53(5): 687-693
 Lingli Jiang, Hang Fan, Ming Qiao, et al. A study on ESD performance of LDMOS with source-bulk layout structure optimization[J]. Journal of Semiconductors, 2013, 12: 44-48
 Lingli Jiang, Ming Qiao, Zhaoji Li, et al. A novel double RESURF LDMOS with optimized ESD robustness[C]. International Conference on Communications, Circuits and Systems (ICCCAS), Chengdu, China, 2009: 638-640
 Guangxing Wan, Tianli Duan, Shuxiang Zhang, Lingli Jiang*, et al. Overshoot Stress on Ultra-thin HfO2 High-k Layer and Its Impact on Lifetime Extraction[J]. IEEE Electron Device Letters, IEEE Electron Device Letters, 2015, 36(12): 1267-1270.
 Jiang Lingli, Conventional AlGaN/GaN Heterojunction Field-Effect Transistors. Chapter of “Gallium Nitride Power Devices”, Pan Stanford Publishing Pte. Ltd., 2017: 93-109
Office: SUSTC, 1088 Xue-Yuan RoadNanshan, Shenzhen
Phone (o): 88018560